The aim of this project is to design and implement a functional 32-bit multi-cycle MIPS processor using VHDL, simulating the behavior of a real CPU by executing a subset of the MIPS instruction set. The project involves constructing and connecting essential hardware components—including memory, register file, ALU, control unit, and intermediate registers—and coordinating their operation across multiple clock cycles using a finite state machine (FSM). This practical assignment reinforces core concepts in digital design, hardware architecture, and control signal generation, while also developing skills in modular VHDL implementation, simulation, and system-level integration.
**MIPS** is an architecture developed in the 1980s. It is widely used in academic settings to teach computer architecture concepts due to its simplicity and clean instruction format.
MIPS uses a load/store architecture, meaning that only load (lw) and store (sw) instructions access memory, while all other operations are performed on registers. Its instruction set is fixed-length (32-bit) and follows a streamlined, predictable design that makes it easy to pipeline—an essential feature in modern CPU performance.
MIPS instructions fall into three main types:
add, sub)lw, sw, beq)j, jal)